TFT array substrates in which TFT (Thin Film transistor) elements are provided on an insulating substrate have been widely used in display devices (such as liquid crystal panels), and sensor devices. The TFT elements are connected with wirings at their electrodes.
Specifically, a TFT element is connected with a corresponding gate bus line at its gate electrode, and connected with a corresponding source bus line at its source electrode.
Moreover, in case where the TFT array substrate is used in a liquid crystal panel, the TFT element is connected with a pixel electrode at its drain electrode.
In case where the TFT elements are arrayed in matrix, the gate bus lines and the source bus lines are provided perpendicular to each other on the insulating substrate. In this case, the gate bus lines and source bus lines are provided in different layers on the insulating substrate between which an insulating layer is provided, lest the gate bus lines and source bus lines be electrically connected with each other.
(Schematic Configuration of TFT Array Substrate)
Next, a configuration of the TFT array substrate is schematically described below.
FIG. 12 is a plane view schematically illustrating a configuration of a TFT array substrate 20.
As illustrated in FIG. 12, the TFT array substrate 20 has a display area 22 in a central portion thereof in a plane view. In the display area, TFT elements and pixel electrodes correspondingly connected to the TFT elements are arrayed in matrix.
An area around the display area 22 and in the vicinity of substrate edges 26 of the TFT array substrate 20 is a periphery area 24. In the periphery area 24, a driver circuit 60 and the like are provided.
One specific example of the driver circuit 60 is a gate driver circuit. FIG. 12 illustrates an exemplary configuration in which the driver circuit 60 is provided in the periphery area 24 on either side of the display area 22 in a horizontal direction (the X direction in FIG. 12).
In this configuration, the driver 60 is connected with the TFT elements (not illustrated) in the display area 22 via wirings such as the gate bus lines 42.
Moreover, the TFT array substrate 20 illustrated in FIG. 12 is provided with a driver 62 in the periphery area 24 on one of both sides of the display area 22 in the vertical direction (the Y direction in FIG. 12). The driver 62 and the driving circuits 60 are connected via a gate driver circuit signal wiring 46 such as a clock wiring. Moreover, the driver 62 is connected with the TFT element (not illustrated) in the display area 22 via wirings such as the source bus lines 44.
Moreover, the TFT array substrate 20 are assembled together with a counter electrode (not illustrated) via a seal 90, thereby constituting a liquid crystal display panel 10. The seal 90 is provided in a frame-like shape along and inside the substrate edges 26 of the TFT array substrate 20.
(Periphery Area)
Next, based on FIG. 13, the periphery area 24 is described in more details.
FIG. 13 is a plane view schematically illustrating a configuration of the periphery area 24.
As illustrated in FIG. 13, the periphery area 24 is provided with not only the driver circuits 60 but also various wirings connected with the driver 62. The wirings are provided between the driver circuits 60 and substrate edges 26 of an insulating substrate 16. FIG. 13 illustrates an example of the TFT array substrate 20 in which a low-potential-side power supply wiring 70, a clock wiring 72, and branch wirings 74 are provided as the wirings. Among the wirings, the low-potential-side power supply wiring 70 and the clock wiring 72 are extended in the vertical direction (Y direction) and the branch wirings 74 are extended in the horizontal direction (X direction). Further, the low-potential-side power supply wiring 70 and the clock wiring 72 are electrically connected with the driver circuit 60 via the branch wirings 74, correspondingly.
(Metal Materials Etc.)
Next, metal materials etc. for forming the wirings are explained below.
The low-potential-side power supply wiring 70 and the clock wiring 72 extended in the Y direction are provided on the insulating substrate in such a manner that the low-potential-side power supply wiring 70 and the clock wiring 72 extended in the Y direction are provided in a layer different from another layer thereon in which the branch wirings 74 extended in the X direction are provided. And, they are formed from different metal materials.
FIG. 14 is a cross sectional view schematically illustrating a configuration of the TFT array substrate 20.
As illustrated in FIG. 14, it is generally configured such that a first metal material M1, a first insulating material I1, a second metal material M2, a second insulating material I2, and a third metal material M3 are laminated in this order on the insulating substrate 16. The first metal material M1 is a material from which the gate bus lines 42 are formed. The first insulating material I1 is a material from which a gate insulating film 50 is formed. The second metal material M2 is a material from which the source bus lines 44 are formed. The second insulating material I2 is a material from which an interlayer insulating film 52 is formed. And the third metal material M3 is a material from which pixel electrodes 48 are formed.
The low-potential-side power supply wiring 70 and the clock wiring 72 are formed from the first metal material M1, and the branch wirings 74 are formed from the second metal material M2.
With this configuration, a wiring extended in the X direction can be crossed easily with a wiring extended in the Y direction, without electrically connecting these wirings as illustrated in an intersection part 82 in FIG. 13.
On the other hand, it is necessary to provide a contact hole in order to establish electrical connection between a wiring extended in the X direction and a wiring extended in the Y direction, as illustrated at a connection portion 80 in FIG. 13.
(Patent Literature 1)
One conventional configuration of such a contact hole is one as illustrated in Patent Literature 1, for example.
FIG. 15 is a view illustrating an amorphous silicon thin film transistor liquid crystal display panel as described in Patent Literature 1.
As illustrated in FIG. 15, a main wiring 150 and a gate electrode 160 are connected electrically via a contact hole 100 provided in a connection portion 80.